IC Delayer

Remove the multi-layer structure of the chip by proprietary techniques to enable clearly presenting circuit layout structure of each layer for later experiments.

IC delayer technology is widely employed in failure analysis and reverse engineering. A failure, such as local burnout, can be exposed for detection through layer-by-layer removal. Delayering is able to systematically expose each IC layer for structure inspection.

What NRPL can do for you

Reverse analysis by delayering metal layer with proprietary techniques (dry/wet) etching and polishing, zoom in using optical microscope (100x ~ 1500x) or sophisticated instruments like Scanning electron microscope or Transmission electron microscope for greater magnification to identify metal leakage or burn out, metal short among other errors.

Reverse Engineering Analysis

• Ordinary Cu, Al metallic layer delayer
• Gate oxide pinhole (with SEM or TEM analysis)
• FinFET process

SEM / TEM

• Smaller process or micro error inspection
• 3D substrate review over FinFET process

EDS / EDX / EDAX for elemental analysis